8.50 Opening remarks
9.00 Vincent M. Donnelly
University of Houston, USA;
Selected Diagnostic Methods for Plasmas and Plasma-Surface Interactions – Invited
9.40 M.C.M. van de Sanden, M.A. Blauw, R.F. Rumphorst, M. Creatore and W.M.M. Kessels
Plasma & Materials Processing Group, Department of Applied Physics,
Eindhoven University of Technology, Eindhoven, The Netherlands
Materials processing with the expanding thermal plasma technique using controlled ion flux and energy
10.00 T. Chevolleau1, M. Darnon1, T. David2, N. Posseme2 and O. Joubert1
1CNRS/LTM, (CEA/LETI-Minatec), 17 rue des martyrs, F38054 Grenoble cedex 09,
2CEA/LETI-Minatec, 17 rue des martyrs, F38054 Grenoble cedex 09
Chamber Walls Coatings During Patterning of Dielectric Damascene Structures With a Metal Hard Mask:
Consequences on Cleaning Strategies
10.20 Coffee break
10.40 E. Stamate
Risø National Laboratory, Technical University of Denmark, Roskilde 4000, Denmark
Etching of silicon by plasma-sheath-lens focused negative ions
10.00 E.V. Danilkin,1,2 D. Shamiryan,2 M.R. Baklanov,2 W. Boullart2 and G.Y. Krasnikov1
1MIKRON, 12/1 Pervyi Zapadny Proezd, Zelenograd, 124460 Moscow, Russia
2IMEC vzw, Kapeldreef 75, 3001 Heverlee, Belgium
Influence of quartz window temperature on plasma composition during STI etch
11.20 P.M. Gevers, H.C.W. Beijerinck, M.C.M. van de Sanden, and W.M.M. Kessels
Dept. of Applied Physics, Eindhoven University of Technology
P.O. Box 513, 5600 MB, Eindhoven, The Netherlands
Ion-radical synergy in HfO2 etching studied in a beam experiment
11.40 F. Soberon and M. Tipaka
Lexas Research, Invent Centre, Dublin City University, Ireland
Novel plasma monitoring technique based on modulated optical emission from
the processing discharge
12.00 Lunch break
14.00 Tetsuya Tatsumi
Sony, Japan;
Quantitative control of plasmas for low-k integration – Invited
14.40 M.Darnon1, T.Chevolleau1, N.Posseme2, T.David2, C.Licitra2, J.Torrès3, O.Joubert1
1CNRS/LTM, (CEA/LETI-Minatec), 17 rue des martyrs, F38054 Grenoble cedex 09
2CEA/LETI-Minatec, 17 rue des martyrs, F38054 Grenoble cedex 09
3 STMicroelectronics, Central R&D, 850 rue J. Monnet, F38926, Crolles cedex
Porous SiOCH Modifications by O2, NH3 and CH4 Plasmas Used as Ashing and Pore Sealing Steps
15.00 A. M. Urbanowicz1,2, D. Shamiryan1, D. Kim3, and M. R. Baklanov1
1IMEC, Leuven, Belgium
2Wroclaw University of Technology, Wroclaw, Poland
3Samsung Electronics, Semiconductor R&D Center, Kyunggi-do, South Korea
Effect of Helium Plasma on Low-k damage during Dry Resist Strip
15.20 F. Bailly1,3, A. Jacquier2,3 , M. Darnon4, T. David2, T. Chevolleau4 and C. Cardinaud1
1CNRS/IMN, 2 rue de la Houssinière, 44322 Nantes cedex 03, France
2CEA/LETI-Minatec, 17 rue des martyrs, 38054 Grenoble cedex 09, France
3STMicroelectronics, Central R&D, 850 rue J. Monnet, 38926 Crolles cedex, France
4CNRS/LTM, 17 rue des martyrs, 38054 Grenoble cedex 09, France
Surface Roughening and modification of Porous SiOCH in Fluorocarbon based Plasmas
15.40 Coffee break
16.00 Annemie Bogaerts
University of Antwerp, Belgium;
Computer modeling of etch plasmas: capacitively coupled and inductively coupled rf discharges – Invited
16.40 M. Hauguth1, V. Ishshuk1, D. Dreßler1, T. Danz1, B. Volland1, I.W. Rangelow1, M Cooke2, G Chance2, A York2,
A Goodyear2, G Hassall2 S Daniels3, J Lawler3, D Kavanagh3, E Gogolides4, G Kokkoris4, E Geka4, N Vourdas4,
V Constantoudis4, P Angelikopoulos4 G Mpoulousis4, K Tsougen4, A Panagiotopoulos4, G Xidi4, H Hartmann5, A Petrashenko5,
C Ivanov6, V Gueorguiev6
1Technische Universität Ilmenau, Germany, 2Oxford Instruments Plasma Technology,Yatton, UK, 3Dublin City University, Ireland
4IMEL/NCSR Demokritos, Athens,Greece, 5S3 solutions GmbH, Germany, 6ISMA, Bulgaria
nanoPlasma – nanoscale plasma etching: simulation of the profile evolution of high aspect ratio features
17.00 Poster session with beer tasting
19.00 End of day
9.00 Deirdre L. Olynick
Lawrence Berkeley National Laboratory, USA;
Nanoscale Pattern Transfer for Nanoscience – Invited
9.40 A.P. Milenin, D. Zschech1, M. Steinhart
Max Planck Institute of Microstructure Physics, Halle, Germany
1Deutsches Institut für Normung, Berlin, Germany
Nanostructuring using PMMA/PS block copolymer lithography and plasma etching
10.00 C.C.Welch1 and B.Bilenberg2,
1 Oxford Instruments Plasma Technology, North End, Yatton, Bristol BS49 4AP, UK
Tel +44 1934 837000, Fax +44 1934 837001, e-mail colin.welch@oxinst.co.uk
2NIL Technology, Oersteds Plads, DTU Building 347, DK-2800 Kongens Lyngby, Denmark
ICP Etch Processes for Nanoimprint Lithography
10.20 Coffee break
10.40 Olivier Joubert
CNRS LTM, France;
Plasma Etching Challenges involved in Gate Stack Patterning for 45 nm technological
nodes and below – Invited
11.20 M. Demand, V. Paraschiv, D. Shamiryan, C. Vrancken, S. Brus, A. Veloso and W. Boullart
IMEC, Kapeldreef 75, 3001 Leuven, Belgium
Dry etch of Yb- doped poly-Si gates for low Vt FUSI devices
11.40 T. Morel,1 S. Barnola2 and O.Joubert3
1STMicroelectronics Crolles2, 850 rue Jean Monnet 38926 Crolles cedex
2CEA-LETI Grenoble
3LTM/CNRS
Tungsten alloy etch characterization for sub 45nm metal gate
12.00 Lunch break
13.40 D. Hamada, K. Nakamura, K. Eriguchi, K. Ono
Kyoto University, Yoshida-Honmachi, Sakyo-ku, Kyoto 606-8501, Japan
Etching of high-k dielectric HfO2 films in BCl3-containing plasmas without rf biasing
14.00 V. Paraschiv, 1 J. Hooker, 2 W. Boullart1
1IMEC, Kapeldreef 75, 3001 Leuven, Belgium.
2NXP Semiconductors Belgium, 75 Kapeldreef, 3001 Leuven, Belgium
Integration of Molybdenum Based Layers as Metal Gates: Etch Process and Its Interdependence
with Integration Stack Structure
14.20 Y. S. Chae, D. Y. Lee, C. H. Shin, G. J. Min, C. J. Kang and J. T. Moon
Process Development Team, Semiconductor R&D center, Samsung Electronics, San #16, Banwol-Dong,
Hwasung-City, Gyenggi-Do, 445-701, Korea
Effect of Plasma Treatment on Double Patterning Technique
14.40 Judy Wang, Shing-Li sung, Zhifeng Sui, Eda Tencel, Ajey Joshi, Peter Hseih, Shawming Ma, Jingbao Liu,
Subhash Deshmukh Etch Product Business Group, Dielectric Etch Division, Applied Materials
Shrink and Control Critical Dimension Using Dielectric Etch Chamber for 45nm Technology and Beyond
15.00 Coffee break
15.20 Karen Reinhardt
Cameo Consulting, USA;
Stripping and Cleaning: The Tenacity of Plasma Processing – Invited
16.00 Mansi Bhargava, 1 Aseem Srivastava,2 and John C. Wolfe1
1Department of Electrical and Computer Engineering and the Nanosystem Manufacturing Center,
University of Houston, Houston, TX 772042 Axcelis Technologies, 108 Cherry Hill Drive, Beverly, MA 01915
High Dose Implant Ash using a Medium-Pressure, High Power Plasma Jet
16.20 K Han1, S. Luo1, P. Geissbühler1, Q. Han1, I. Berry1, R. Sonnemans1, V. Grimm2 and C. Krueger2
1Axcelis Technologies, Inc., Beverly, MA 01915, USA
2AMD Fab36 L.L.C. & Co. KG, D-01109 Dresden, Germany
Non-fluorine plasma strip of HDI resist for 45nm node
16.40 Stephen Savas, Stephen Hyatt, Vijay Vaniapura, Reinhold Rieder, Robert Weber, Qin Ce, Bob Elliston,
Chevan Goonetilleke, and Hai-Au Phan-Vu
Mattson Technology, 47131 Bayside Parkway, Fremont, CA. 94538, USA
Implanted Resist Strip and Clean Processes Meeting ITRS Requirements for silicon loss
17.00 E. Kesters1, M.Claes1, M. Lux1, Q.T. Le1, G. Vereecke1, A. Franquet1, T. Conard1, P.W. Mertens1,
P. Adriaensens2, R. Carleer2, J.J. Biebuyk3, P. Van Veltem3 and S. Bebelman3
1 IMEC vzw, Kapeldreef 75, 3001 Heverlee, Belgium
2 Universiteit Hasselt, IMO Division Chemistry, Agoralaan, 3590 Diepenbeek, Belgium
3UCL, Lab. Des Hauts Polymères, Croix du Sud 1, 1348 Louvain-La-Neuve, Belgium
Characterization of post-etch photoresists used in metal hardmask and photoresist mask patterning schemes
17.20 Closing remarks
17.30 End of Workshop